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1 cat28f001 1 megabit cmos boot block flash memory features n fast read access time: 70/90/120/150 ns n on-chip address and data latches n blocked architecture one 8 kb boot block w/ lock out ? top or bottom locations two 4 kb parameter blocks one 112 kb main block n low power cmos operation n 12.0v 5% programming and erase voltage n automated program & erase algorithms n high speed programming n commercial, industrial and automotive temperature ranges 28f001 f01 n deep powerdown mode 0.05 m a i cc typical 0.8 m a i pp typical n hardware data protection n electronic signature n 100,000 program/erase cycles and 10 year data retention n jedec standard pinouts: 32 pin dip 32 pin plcc 32 pin tsop n reset/deep power down mode i/o 0 Ci/o 7 i/o buffers ce, oe logic sense amp data latch erase voltage switch command register ce oe we voltage verify switch address latch y-decoder x-decoder y-gating 8k-byte boot block 4k-byte parameter block 4k-byte parameter block 112k-byte main block a 0 Ca 16 write state machine address counter status register comparator program voltage switch rp block diagram description the cat28f001 is a high speed 128k x 8 bit electrically erasable and reprogrammable flash memory ideally suited for applications requiring in-system or after sale code updates. the cat28f001 has a blocked architecture with one 8 kb boot block, two 4 kb parameter blocks and one 112 kb main block. the boot block section can be at the top or bottom of the memory map and includes a reprogram- ming write lock out feature to guarantee data integrity. it is designed to contain secure code which will bring up the system minimally and download code to other loca- tions of cat28f001. the cat28f001 is designed with a signature mode which allows the user to identify the ic manufacturer and device type. the cat28f001 is also designed with on- chip address latches, data latches, programming and erase algorithms. the cat28f001 is manufactured using catalysts ad- vanced cmos floating gate technology. it is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. the device is available in jedec approved 32-pin plastic dip, plcc or tsop packages. ? 1998 by catalyst semiconductor, inc. characteristics subject to change without notice licensed intel second source doc. no. 25071-00 2/98 f-1
cat28f001 2 doc. no. 25071-00 2/98 f-1 pin configuration dip package (p) tsop package (standard pinout) (t) 28f001 f03 pin functions pin name type function a 0 Ca 16 input address inputs for memory addressing i/o 0 Ci/o 7 i/o data input/output ce input chip enable oe input output enable we input write enable v cc voltage supply v ss ground v pp program/erase voltage supply rp input power down 28f001 f02 plcc package (n) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 v ss i/o 2 i/o 1 i/o 0 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 12 a 15 a 16 v pp v cc we rp a 14 a 13 a 8 a 9 a 11 i/o 0 i/o 1 i/o 2 v ss i/o 6 i/o 5 i/o 4 i/o 3 13 14 15 16 20 19 18 17 9 10 11 12 24 23 22 21 a 3 a 2 a 1 a 0 oe a 10 ce i/o 7 a 7 a 6 a 5 a 4 5 6 7 8 1 2 3 4 v pp a 16 a 15 a 12 a 13 a 8 a 9 a 11 28 27 26 25 32 31 30 29 v cc we rp a 14 a 7 a 6 a 5 a 4 5 6 7 8 a 3 a 2 a 1 a 0 9 10 11 12 i/o 0 13 a 14 a 13 a 8 a 9 29 28 27 26 a 11 oe a 10 ce 25 24 23 22 i/o 7 21 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 i/o 6 14 15 16 17 18 19 20 4321323130 a 12 a 15 a 16 v pp v cc we rp
cat28f001 3 doc. no. 25071-00 2/98 f-1 absolute maximum ratings* temperature under bias ................... C55 c to +95 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to ground (1) ........... C2.0v to +v cc + 2.0v (except a 9 , rp , oe , v cc and v pp ) voltage on pin a 9 , rp and oe with respect to ground (1) ................... C2.0v to +13.5v v pp with respect to ground during program/erase (1) .............. C2.0v to +14.0v v cc with respect to ground (1) ............ C2.0v to +7.0v package power dissipation capability (t a = 25 c) .................................. 1.0 w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma reliability characteristics symbol parameter min. max. units test method n end (3) endurance 100k cycles/byte mil-std-883, test method 1033 t dr (3) data retention 10 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 capacitance t a = 25 c, f = 1.0 mhz limits symbol test min max. units conditions c in (3) input pin capacitance 8 pf v in = 0v c out (3) output pin capacitance 12 pf v out = 0v c vpp (3) v pp supply capacitance 25 pf v pp = 0v note: (1) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
cat28f001 4 doc. no. 25071-00 2/98 f-1 d.c. operating characteristics v cc = +5v 10%, unless otherwise specified limits symbol parameter min. max. unit test conditions i li input leakage current 1.0 m av in = v cc or v ss v cc = 5.5v i lo output leakage current 10 m av out = v cc or v ss , v cc = 5.5v i sb1 v cc standby current cmos 100 m a ce = v cc 0.2v = rp v cc = 5.5v i sb2 v cc standby current ttl 1.5 ma ce = rp = v ih , v cc = 5.5v i ppd v pp deep powerdown current 1.0 m a rp = gnd 0.2v i cc1 v cc active read current 30 ma v cc = 5.5v, ce = v il , i out = 0ma, f = 8 mhz i cc2 (1) v cc programming current 20 ma v cc = 5.5v, programming in progress i cc3 (1) v cc erase current 20 ma v cc = 5.5v, erase in progress i pps v pp standby current 10 m av pp < v cc 200 m av pp > v cc i pp1 v pp read current 200 m av pp = v pph i pp2 (1) v pp programming current 30 ma v pp = v pph , programming in progress i pp3 (1) v pp erase current 30 ma v pp = v pph , erase in progress v il input low level C0.5 0.8 v v ol output low level 0.45 v i ol = 5.8ma, v cc = 4.5v v ih input high level 2.0 v cc +0.5 v v oh output high level 2.4 v i oh = 2.5ma, v cc = 4.5v v id a 9 signature voltage 11.5 13.0 v a 9 = v id i id a 9 signature current 500 m aa 9 = v id i ccd v cc deep powerdown current 1.0 m a rp = gnd 0.2v i cces v cc erase suspend current 10 ma erase suspended ce = v ih i ppes v pp erase suspend current 300 m a erase suspended v pp =v pph note: (1) this parameter is tested initially and after a design or process change that affects the parameter.
cat28f001 5 doc. no. 25071-00 2/98 f-1 supply characteristics limits symbol parameter min max. unit v lko v cc erase/write lock voltage 2.5 v v cc v cc supply voltage 4.5 5.5 v v ppl v pp during read operations 0 6.5 v v pph v pp during erase/program 11.4 12.6 v v hh rp, oe unlock voltage 11.4 12.6 v a.c. characteristics, read operation v cc = +5v 10%, unless otherwise specified jedec standard 28f001-90 (7) 28f001-12 (7) 28f001-15 (7) symbol symbol parameter min. max. min. max. min. max. unit t avav t rc read cycle time 90 120 150 ns t elqv t ce ce access time 90 120 150 ns t avqv t acc address access time 90 120 150 ns t glqv t oe oe access time 35 50 55 ns -t oh output hold from address oe/ce change 0 0 0 ns t glqx t olz (1)(6) oe to output in low-z 0 0 0 ns t elqx t lz (1)(6) ce to output in low-z 0 0 0 ns t ghqz t df (1)(2) oe high to output high-z 30 30 30 ns t ehqz t hz (1)(2) ce high to output high-z 35 55 55 ns t phqv t pwh rp high to output delay 600 600 600 ns 28f001-70 (8) min. max. 0 0 0 70 70 70 27 30 55 600 5108 fhd f05 note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) output floating (high-z) is defined as the state where the external data line is no longer driven by the output buffer. (3) input rise and fall times (10% to 90%) < 10 ns. (4) input pulse levels = 0.45v and 2.4v. for high speed input pulse levels 0.0v and 3.0v. (5) input and output timing reference = 0.8v and 2.0v. for high speed input and output timing reference = 1.5v. (6) low-z is defined as the state where the external data may be driven by the output buffer but may not be valid. (7) for load and reference points, see fig. 1 (8) for load and reference points, see fig. 2 1.3v device under test 1n914 3.3k c l = 100 pf out c l includes jig capacitance input pulse levels reference points 2.0 v 0.8 v 2.4 v 0.45 v 5108 fhd f03a figure 1. a.c. testing input/output waveform (3)(4)(5) testing load circuit (example) 1.3v device under test 1n914 3.3k c l = 30 pf out c l includes jig capacitance 5108 fhd f04 input pulse levels reference points 3.0 v 0.0 v 1.5 v 5108 fhd f03 figure 2. highspeed a.c. testing input/output waveform(3)(4)(5) testing load circuit (example)
cat28f001 6 doc. no. 25071-00 2/98 f-1 a.c. characteristics, program/erase operation v cc = +5v 10% jedec standard 28f001-70 28f001-90 28f001-12 28f001-15 symbol symbol parameter min. max. min. max. min. max. min. max. unit t avav t wc write cycle time 70 90 120 150 ns t avwh t as address setup to we going high 35 40 40 40 ns t whax t ah address hold time from we going high 10 10 10 10 ns t dvwh t ds data setup time to we going high 40 40 40 ns t whdx t dh data hold time from we going high 10 10 10 ns t elwl t cs ce setup time to we going low 0 0 0 ns t wheh t ch ce hold time from we going high 0 0 0 ns t wlwh t wp we pulse width 40 40 40 ns t whwl t wph we high pulse width 10 10 10 ns t whgl write recovery time before read 0 0 0 m s t phwl t ps (1) rp high recovery to we going low 480 480 480 ns t phhwh t phs (1) rp v hh setup to we going high 100 100 100 ns t vpwh t vps (1) v pp setup to we going high 100 100 100 ns t whqv1 duration of programming operations 15 15 15 15 m s t whqv2 duration of erase operations (boot) 1.3 1.3 1.3 1.3 sec t whqv3 duration of erase operations (parameter) 1.3 1.3 1.3 1.3 sec t whqv4 duration of erase operations (main) 3 3 3 3 sec t qvvl t vph (1) v pp hold from valid status reg data 0 0 0 0 ns t qvph t phh (1) rp v hh hold from status reg data 0 0 0 0 ns t phbr (1) boot block relock delay 100 100 100 100 ns t ghhwl oe v hh setup to we going low 480 480 480 480 ns t whgh oe v hh hold from we high 480 480 480 480 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. 35 10 0 0 35 10 0 480 100 100
cat28f001 7 doc. no. 25071-00 2/98 f-1 erase and programming performance 28f001-70 28f001-90 28f001-12 28f001-15 parameter min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit boot block erase time 2.10 14.9 2.10 14.9 2.10 14.9 2.10 14.9 sec boot block program time 0.15 0.52 0.15 0.52 0.15 0.52 0.15 0.52 sec parameter block erase time 2.10 14.6 2.10 14.6 2.10 14.6 2.10 14.6 sec parameter block program time 0.07 0.26 0.07 0.26 0.07 0.26 0.07 0.26 sec main block erase time 3.80 20.9 3.80 20.9 3.80 20.9 3.80 20.9 sec main block program time 2.10 7.34 2.10 7.34 2.10 7.34 2.10 7.34 sec chip erase time 10.10 65 10.10 65 10.10 65 10.10 65 sec chip program time 2.39 8.38 2.39 8.38 2.39 8.38 2.39 8.38 sec function table (1) pins mode rp rp rp rp rp ce ce ce ce ce oe oe oe oe oe we we we we we v pp i/o notes read v ih v il v il v ih xd out output disable v ih v il v ih v ih x high-z standby v ih v ih x x x high-z signature (mfg) v ih v il v il v ih x 31h a 0 = v il , a 9 = 12v signature (device) v ih v il v il v ih x 94h-28f001t a 0 = v ih , a 9 = 12v 95h-28f001b write cycle v ih v il v ih v il xd in during write cycle deep power down v il xxxx high-z write command table commands are written into the command register in one or two write cycles. write cycles also internally latch addresses and data required for programming and erase operations. first bus cycle second bus cycle mode operation address d in operation address d in d out read array/reset write x ffh program setup/ write a in 40h write a in d in program 10h read status reg. write x 70h read x st. reg. data clear status reg. write x 50h erase setup/erase write block ad 20h write block ad d0h confirm erase suspend/ write x b0h write x d0h erase resume read sig (mfg) write x 90h read 0000h 31h read sig (dev) write x 90h read 0001h 94h-28f001t 95h-28f001b note: (1) logic levels: x = logic do not care (v ih , v il , v ppl , v pph )
cat28f001 8 doc. no. 25071-00 2/98 f-1 read operations read mode the cat28f001 memory can be read from any of its blocks (boot block, main block or parameter block), status register and signature information by sending the read command mode to the command register. cat28f001 automatically resets to read array mode upon initial device power up or after exit from deep power down. a read operation is performed with both ce and oe low and with rp and oe high. vpp can be either high or low. the data retrieved from the i/o pins reflects the contents of the memory location correspond- ing to the state of the 17 address pins. the respective timing waveforms for the read operation are shown in figure 3. refer to the ac read characteristics for specific timing parameters. signature mode the signature mode allows the user to identify the ic manufacturer and the type of the device while the device resides in the target system. this mode can be activated in either of two ways; through the conventional method of applying a high voltage (12v) to address pin a9 or by sending an instruction to the command register (see write operations). the conventional method is entered as a regular read mode by driving the ce and oe low (with we high), and applying the required high voltage on address pin a9 while the other address line are held at vil. a read cycle from address 0000h retrieves the binary code for the ic manufacturer on outputs i/o 7 to i/o 0 : catalyst code = 0011 0001 (31h) a read cycle from address 0001h retrieves the binary code for the device on outputs i/o 7 to i/o 0 : cat28f001t = 1001 0100 (94h) cat28f001b = 1001 0101 (95h) standby mode with ce at a logic-high level, the cat28f001 is placed in a standby mode where most of the device circuitry is disabled, thereby substantially reducing power con- sumption. the outputs are placed in a high-impendance state independent of the oe status. deep power-down when rp is at logic-low level, the cat28f001 is placed in a deep power-down mode where all the device circuitry are disabled, thereby reducing the power con- sumption to 0.25 m w. figure 3. a.c. timing for read operation 28f001 f05 addresses ce (e) oe (g) we (w) data (i/o) high-z power up standby device and address selection ouputs enabled data valid standby address stable output valid t avqv (t acc ) t elqx (t lz ) t glqx (t olz ) t glqv (t oe ) t elqv (t ce ) t oh t ghqz (t df ) t ehqz t avav (t rc ) power down high-z t phqv (t pwh ) rp (p)
cat28f001 9 doc. no. 25071-00 2/98 f-1 write operations the following operations are initiated by observing the sequence specified in the write command table. read array the device can be put into a read array mode by initiating a write cycle with ffh on the data bus. the device is also in a standard read array mode after the initial device power up and when comes out of the deep power-down mode. signature mode an alternative method for reading device signature (see read operations signature mode), is initiated by writing the code 90h into the command register. a read cycle from address 0000h with ce and oe low (and we high) will output the device signature. catalyst code = catalyst code = 0011 0001 (31h) a read cycle from address 0001h retrieves the binary code for the device on outputs i/o 7 to i/o 0 : cat28f001t = 1001 0100 (94h) cat28f001b = 1001 0101 (95h) to terminate the operations, it is necessary to write another valid command into the register. status register the 28f001 contains an 8-bit status register. the status register is polled to check for write or erase completion or any related errors. the status register may be read at any time by issuing a read status register (70h) command. all subsequent read opera- tions output data from the status register, until another valid command is issued. the contents of the status register are latched on the falling edge of oe or ce , whichever occurs last in the read cycle. oe or ce must be toggled to vih before further reads to update the status register latch. the erase status (sr.5) and program status (sr.4) are set to 1 by the wsm and can only be reset issuing clear status register (50h) these two bits can be polled for failures, thus allowing more flexibility to the designer when using the cat28f001. also, vpp status (sr.3) when set to 1 must be reset by system software before any further byte programs or block erases are attempted. erase setup/erase confirm erase is executed one block at a time, initiated by a two cycle command sequence. the two cycle command sequence provides added security against accidental block erasure. during the first write cycle, a command 20h (erase setup) is first written to the command register, followed by the command d0h (erase con- firm). these commands require both appropriate com- mand data and an address within block to be erased. also, block erasure can only occur when vpp= vpph. block preconditioning, erase and verify are all handled internally by the write state machine, invisible to the system. after receiving the two command erase se- quence the cat28f001 automatically outputs status register data when read (fig.5). the cpu can detect the completion of the erase event by checking if the sr.7 of the status register is set. sr.5 will indicate whether the erase was successful. if an erase error is detected, the status register should be cleared. the device will be in the status register read mode until another command is issued. erase suspend/erase resume the erase suspend command allows erase sequence interruption in order to read data from another block of memory. once the erase sequence is started, writing the erase suspend command (b0h) to the command register requests that the wsm suspend the erase sequence at a predetermined point in the erase algo- rithm. the cat28f001 continues to output status reg- ister data when read, after the erase suspend command is written to it. polling the wsm status and erase suspend status bits will determine when the erase operation has been suspended (both will be set to 1s). the device may now be given a read array com- mand, which allows any locations 'not within the block being erased' to be read. also, you can either perform a read status register or resume the erase operation by sending erase resume (d0h), at which time the wsm will continue with the erase sequence. the erase suspend status and wsm status bits of the status register will be cleared. program setup/program commands programming is executed by a two-write sequence. the program setup command (40h) is written to the com- mand register, followed by a second write specifying the address and data (latched on the rising edge of we ) to be programmed. the wsm then takes over, control- ling the program and verify algorithms internally. after the two-command program sequence is written to it, the cat28f001 automatically outputs status register data when read (see figure 4; byte program flowchart). the cpu can detect the completion of the program event by analyzing the wsm status bit of the status register. only the read status register command is valid while programming is active.
cat28f001 10 doc. no. 25071-00 2/98 f-1 when the status register indicates that programming is complete, the program status bit should be checked. if program error is detected, the status register should be cleared. the internal wsm verify only detects errors for 1s that do not successfully program to 0s. the command register remains in read status register mode until further commands are issued to it. if erase/byte program is attempted while v pp = v ppl , the status bit (sr.5/sr.4) will be set to 1. erase/program attempts while v ppl < v pp < v pph produce spurious results and should not be attempted. embedded algorithms the cat28f001 integrates the quick pulse program- ming algorithm on-chip, using the command register, status register and write state machine (wsm). on- chip integration dramatically simplifies system software and provides processor-like interface timings to the command and status registers. wsm operation, inter- nal program verify, and v pp high voltage presence are monitored and reported via appropriate status register bits. figure 4 shows a system software flowchart for device programming. as above, the quick erase algorithm is now imple- mented internally, including all preconditioning of block data. wsm operation, erase verify and v pp high voltage presence are monitored and reported through the status register. additionally, if a command other than erase confirm is written to the device after erase setup has been written, both the erase status and program status bits will be set to 1. when issuing the erase setup and erase confirm commands, they should be written to an address within the address range of the block to be erased. figure 5 shows a system software flowchart for block erase. the entire sequence is performed with v pp at v pph . abort occurs when rp transitions to v il , or v pp drops to v ppl . although the wsm is halted, byte data is partially programmed or block data is partially erased at the location where it was aborted. block erasure or a repeat of byte programming will initialize this data to a known value. boot block program and erase the boot block is intended to contain secure code which will minimally bring up a system and control program- ming and erase of other blocks of the device, if needed. therefore, additional lockout protection is provided to guarantee data integrity. boot block program and erase operations are enabled through high voltage v hh on either rp or oe , and the normal program and erase command sequences are used. reference the ac waveforms for program/erase. if boot block program or erase is attempted while rp is at v ih , either the program status or erase status bit will be set to 1, reflective of the operation being attempted and indicating boot block lock. program/erase attempts while v ih < rp < v hh produce spurious results and should not be attempted. notes: the write state machine status bit must first be checked to determine program or erase completion, before the program or erase status bits are checked for success. if the program and erase status bits are set to 1s during an erase attempt, an improper command sequence was entered. attempt the operation again. if v pp low status is detected, the status register must be cleared before another program or erase operation is attempted. the v pp status bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates the v pp level only after the program or erase command sequences have been entered and informs the system if v pp has not been switched on. the v pp status bit is not guaranteed to report accurate feedback between v ppl and v pph . sr.7 = write state machine status 1 = ready 0 = busy sr.6 = erase suspend status 1 = erase suspended 0 = erase in progress/completed sr.5 = erase status 1 = error in block erasure 0 = successful block erase sr.4 = program status 1 = error in byte program 0 = successful byte program sr.3 = vpp status 1 = v pp low detect; operation abort 0 = v pp okay sr.2 -sr.0 = reserved for future enhancements these bits are reserved for future use and should be masked out when polling the status register. wsms ess es ps vpps r r r 76543210
cat28f001 11 doc. no. 25071-00 2/98 f-1 bus operation command comments write program data = 40h setup address = bytes to be programmed write program data to be programmed address = byte to be programmed read status register data. toggle oe or ce to update status register check sr.7 standby 1 = ready, 0 = busy repeat for subsequent bytes. full status check can be done after each byte or after a sequence of bytes. write ffh after the last byte programming operation to reset the device to read array mode. bus operation command comments standby check sr.3 1 = v pp low detect standby check sr.3 1 = byte program error sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.3 is only cleared by the clear status register command, in case where multiple bytes are programmed before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. start write 40h, byte address read status register sr.7 = 1? full status check if desired byte program completed status register data read (see above) sr.3 = 0? sr.4 = 0? byte program successful no no write byte address/data full status check procedure no v pp range error byte program error yes yes yes figure 4 byte programming flowchart in-system operation for on-board programming, the rp pin is the most convenient means of altering the boot block. before issuing program or erase confirms commands, rp must transition to v hh . hold rp at this high voltage throughout the program or erase interval (until after status register confirm of successful completion). at this time, it can return to v ih or v il .
cat28f001 12 doc. no. 25071-00 2/98 f-1 bus operation command comments write erase data = 20h setup address = within block to be erased write erase data - d0h address = within block to be erased read status register data. toggle oe or ce to update status register standby check sr.7 1 = ready, 0 = busy repeat for subsequent blocks. full status check can be done after each block or after a sequence of blocks. write ffh after the last block erase operation to reset the device to read array mode. bus operation command comments standby check sr.3 1 = v pp low detect standby check sr.4 both 1 = command sequence error standby check sr.5 1 = block erase error sr.3 must be cleared, if set during a erase attempt, before further attempts are allowed by the write state machine. sr.3 is only cleared by the clear status register command, in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. figure 5 block erase flowchart start write 20h, block address read status register sr.7 = 1? full status check if desired block erase completed status register data read (see above) sr.3 = 0? sr.5 = 0? block erase successful no no write d0h block address full status check procedure no v pp range error block erase error sr.4,5 = 1? yes command sequence error suspend erase? no erase suspend loop yes yes no yes
cat28f001 13 doc. no. 25071-00 2/98 f-1 bus operation command comments write erase data = b0h suspend standby/ read status register ready check sr.7 1 = ready, 0 = busy toggle oe or ce to update status register standby check sr.6 1 = suspended write read array data = ffh read read array data from block other than that being erased. write erase resume data = d0h start write b0h read status register sr.7 = 1? sr.6 = 1? continue erase no done reading? write ffh write d0h no erase has completed yes yes no yes figure 6 block erase suspend/resume flowchart
cat28f001 14 doc. no. 25071-00 2/98 f-1 power up/down protection the cat28f001 offers protection against inadvertent programming during v pp and v cc power transitions. when powering up the device there is no power-on sequencing necessary. in other words, v pp and v cc may power up in any order. additionally v pp may be hardwired to v pph independent of the state of v cc and any power up/down cycling. the internal command register of the cat28f001 is reset to the read mode on power up. power supply decoupling to reduce the effect of transient power supply voltage spikes, it is good practice to use a 0.1 m f ceramic capacitor between v cc and v ss and v pp and v ss . these high-frequency capacitors should be placed as close as possible to the device for optimum decoupling. figure 7. a.c. timing for program/erase operation 28f001 f09 addresses (a) ce ( e ) oe ( g ) we ( w ) data (i/o) rp (p) v pp (v) v il v ih v ppl v pph v il v ih 6.5v v hh v il v ih v il v ih v il v ih t elwl t wheh t avav a in a in t avwh t whax t whgl t whwl t phwl t dvwh t wlwh t whdx t phhwh t qvph t vpwh t qvvl d in d in valid srd d in high z v ih v ih v cc power-up & standby write program or erase setup command automated program or erase delay read status register data write read array command write valid address & data (program) or erase confirm command v il v il t whqv 1, 2, 3, 4
cat28f001 15 doc. no. 25071-00 2/98 f-1 alternate ce-controlled writes v cc = +5v 10%, unless otherwise specified jedec standard 28f001-70 28f001-90 28f001-12 28f001-15 symbol symbol parameter min. max. min. max. min. max. min. max. uni t t avav t wc write cycle time 70 90 120 150 ns t aveh t as address setup to ce going high 35 40 40 40 ns t ehax t ah address hold time from ce going high 10 10 10 10 ns t dveh t ds data setup time to ce going high 35 40 40 40 ns t ehdx t dh data hold time from ce going high 10 10 10 10 ns t wlel t ws we setup time to ce going low 0 0 0 0 ns t ehwh t wh we hold time from ce going high 0 0 0 0 ns t eleh t cp ce pulse width 35 40 40 40 ns t ehel t eph ce high pulse width 10 10 10 10 ns t ehgl write recovery time before read 0 0 0 0 m s t phel t ps (1) rp high recovery to ce going low 480 480 480 480 ns t phheh t phs (1) rp v hh setup to ce going high 100 100 100 100 ns t vpeh t vps (1) v pp setup to ce going high 100 100 100 100 ns t ehqv1 duration of programming operations 15 15 15 15 m s t ehqv2 duration of erase operations (boot) 1.3 1.3 1.3 1.3 sec t ehqv3 duration of erase operations (parameter) 1.3 1.3 1.3 1.3 sec t ehqv4 duration of erase operations (main) 3 3 3 3 sec t qvvl t vph (1) v pp hold from valid status reg data 0 0 0 0 ns t qvph t phh (1) rp v hh hold from status reg data 0 0 0 0 ns t phbr (1) boot block relock delay 100 100 100 100 ns t ghhwl oe v hh setup to we going low 480 480 480 480 ns t whgh oe v hh hold from we high 480 480 480 480 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter.
cat28f001 16 doc. no. 25071-00 2/98 f-1 figure 8. alternate boot block access method using oe figure 9. alternate ac waveform for write operations write program or erase setup command write valid address and data (program) or erase confirm command automated program or erase delay read status register data v hh v ih v il v ih v il v ih v il d in d in t ghhwl t whgh valid sr data oe we data addresses ce (e) oe ( a ) we (w) data i/o rp ( p ) v pp (v) v il v ih v ppl v pph v il v ih 6.5v v hh v il v ih v il v ih v il v ih t wlel t ehwh t avav a in a in t aveh t ehax t ehgl t ehel t phel t dveh t eleh t ehdx t phheh t qvph t vpeh t qvvl d in d in valid srd d in high z v ih v ih v cc power-up & standby write program or erase setup command automated program or erase delay read status register data write read array command write valid address & data (program) or erase confirm command v il v il t ehqv 1, 2, 3, 4
cat28f001 17 doc. no. 25071-00 2/98 f-1 ordering information 28f001 f12 prefix device # suffix 28f001 p it product number temperature range blank = commercial (0? - 70?c) i = industrial (-40? - 85?c) a = automotive (-40? - 105?c)* tape & reel t: 500/reel package n: plcc p: pdip t: tsop (8mmx20mm) speed 70: 70ns 90: 90 ns 12: 120 ns 15: 150 ns -90 cat b boot block b: bottom t: to p * -40? to +125?c is available upon request optional company id note: (1) the device used in the above example is a cat28f001pi-90bt (pdip, industrial temperature, 90ns access time, bottom boot blo ck, tape & reel)
cat28f001 18 doc. no. 25071-00 2/98 f-1

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